/*
  ******************************************************************************
  * @file    apt32f172_tc3_ctc.c
  * @author  APT AE Team
  * @version V1.12
  * @date    2019/03/08
  ******************************************************************************
  *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES 
  *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
  *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, 
  *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF 
  *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION 
  *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES 
  *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/ 
#include "apt32f172_tc3_ctc.h"
/* defines -------------------------------------------------------------------*/

/* externs--------------------------------------------------------------------*/

/*************************************************************/
//CTC RESET VALUE
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/  
void CTC_RESET_VALUE(void)									//reset value
{
  	CTC->IDR=CTC_IDR_RST;          				/**< IDR reset value      */
   	CTC->CSSR=CTC_CSSR_RST;		 				/**< CSSR reset value     */	
   	CTC->CEDR=CTC_CEDR_RST;						/**< CEDR reset value     */
	CTC->SRR=CTC_SRR_RST;						/**< SRR reset value      */
	CTC->CR=CTC_CR_RST;							/**< CR reset value       */
	CTC->PRDR=CTC_PRDR_RST;						/**< PRDR reset value     */
	CTC->TIMDR=CTC_TIMDR_RST;					/**< TIMDR reset value    */
	CTC->IMCR=CTC_IMCR_RST;						/**< IMCR reset value     */
	CTC->RISR=CTC_RISR_RST;						/**< RISR reset value     */
	CTC->MISR=CTC_MISR_RST;						/**< MISR reset value     */
	CTC->ICR=CTC_ICR_RST;						/**< ICR reset value      */
}
/*************************************************************/
//CTC IO Init
//EntryParameter:STC16_IO_G
//(0->PD0.0(AF4);1->PC0.2(AF3))
//ReturnValue:NONE
/*************************************************************/
void CTC_IO_Init(U8_T CTC_IO_G )
{
	if(CTC_IO_G==0)
	{
		GPIOD0->CONLR=(GPIOD0->CONLR & 0XFFFFFFF0)|0x00000007;										//CTC_IO_BUZZ(PD0.0->AF4)
	}
	else if(CTC_IO_G==1)
	{
		GPIOC0->CONLR=(GPIOC0->CONLR & 0XFFFFF0FF)|0x00000600;										//CTC_IO_BUZZ(PC0.2->AF3)
	}
}
/*************************************************************/
//CTC CLK CMD
//EntryParameter:NewState
//NewState:DISABLE,ENABLE
//ReturnValue:NONE
/*************************************************************/
void CTC_Clk_CMD(FunctionalStatus NewState)
{
	if(NewState != DISABLE)
	{
		CTC->CEDR |= 0x03;							//enable CTC clk 
	}
	else
	{
		CTC->CEDR &= 0XFFFFFFFE;					//Disable CTC clk 
	}
}
/*************************************************************/
//CTC Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CTC_Int_Enable(void)
{
    INTC_ISER_WRITE(TC3_INT);    
}
/*************************************************************/
//CTC Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CTC_Int_Disable(void)
{
    INTC_ICER_WRITE(TC3_INT);    
}
/*************************************************************/
//CTC Interrupt wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CTC_Wakeup_Enable(void)
{
    INTC_IWER_WRITE(TC3_INT);    
}
/*************************************************************/
//CTC Interrupt wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CTC_Wakeup_Disable(void)
{
    INTC_IWDR_WRITE(TC3_INT);    
}
/*************************************************************/
//CTC Capture INT Configure
//EntryParameter:CTC_INT_X,NewState
//CTC_INT_X:CTC_INT_PEND,CTC_INT_OVF
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/ 
void CTC_INT_CMD(CTC_INT_TypeDef CTC_INT_X , FunctionalStatus NewState)
{
	if (NewState != DISABLE)
	{
		CTC->IMCR |=CTC_INT_X;					//SET
	}
	else
	{
		CTC->IMCR &=(~CTC_INT_X);				//CLR
	}
}
/*************************************************************/
//CTC Interrupt enable
//EntryParameter:CTC_CLK_Source_set_X,CTC_BUZZ_Freq_X,CTC_Count_Period_X,CTC_Count_Mode_set_X
//CTC_CLK_Source_set_X:CTC_CLK_Source_set_EMOSC,CTC_CLK_Source_set_ISOSC
//CTC_BUZZ_Freq_X:CTC_BUZZ_Freq_500Hz,CTC_BUZZ_Freq_1kHz,CTC_BUZZ_Freq_2kHz,CTC_BUZZ_Freq_4kHz
//CTC_Count_Period_X:CTC_Count_Period_4ms,CTC_Count_Period_16ms,CTC_Count_Period_63ms,CTC_Count_Period_125ms
//,CTC_Count_Period_250ms,CTC_Count_Period_500ms,CTC_Count_Period_1s,CTC_Count_Period_PRDR
//CTC_Count_Mode_set_X:CTC_Count_Mode_set_Normal,CTC_Count_Mode_set_Period
//ReturnValue:NONE
/*************************************************************/
void CTC_Config(CTC_CLK_Source_set_TypeDef CTC_CLK_Source_set_X , CTC_BUZZ_Freq_TypeDef CTC_BUZZ_Freq_X ,
			CTC_Count_Period_TypeDef CTC_Count_Period_X )
{
	if(CTC_CLK_Source_set_X==CTC_CLK_Source_set_EMOSC)
	{
		CTC->CSSR&=0XFFFFFFFE;									//选择外部晶振32.768K
	}
	else if(CTC_CLK_Source_set_X==CTC_CLK_Source_set_ISOSC)
	{
		CTC->CSSR|=0x01;										//选择内部副频
	}
	CTC->CR=CTC_Count_Period_X|CTC_BUZZ_Freq_X;
}
/*************************************************************/
//CTC Software Reset 
//EntryParameter:
//ReturnValue:none
/*************************************************************/
void CTC_SoftReset(void)
{
	CTC->SRR=0X01;
} 
/*************************************************************/
//CTC start 
//EntryParameter:
//ReturnValue:none
/*************************************************************/ 
void CTC_Start(void)
{
	delay_nms(100);
	CTC->CR|=0X01;
}
/*************************************************************/
//CTC stop 
//EntryParameter:
//ReturnValue:none
/*************************************************************/ 
void CTC_stop(void)
{
	delay_nms(100);
	CTC->CR&=0Xfffffffe;
}


/******************* (C) COPYRIGHT 2018 APT Chip *****END OF FILE****/